1. Field of the Invention
This invention relates generally to master-slave flip-flop circuits and more particularly is directed to a phase inverter for a master-slave flip-flop circuit to invert the phase of the output signals of the master and slave flip-flop circuits at any desired time by means of a phase inverting signal wherein the tolerance for selecting the pulse width and phase of the phase inverting signal is relatively large.
2. The Prior Art
In PAL color television receivers master-slave flip-flop circuits are frequently used as a circuit to generate switching signals. At certain times the phase of the output signal of the flip-flop circuit must be inverted. A typical master-slave flip-flop circuit includes an input terminal to which an input timing signal is applied. One of the two output terminals of the master flip-flop is connected to one of two input terminals of an AND gate and the other output terminal of the master flip-flop is connected to one of two input terminals of another AND gate. The two output terminals of the AND gates are connected to the SET and RESET terminals of the slave flip-flop. The output terminals of the slave flip-flop are the output terminals of the master-slave flip-flop circuit, and each of these output terminals is connected to one input terminal of each of a second pair of AND gates. The master-slave flip-flop circuit has a signal receiving input terminal connected to the other input terminal of each of the first pair of AND gates, and the same input terminal is connected through an inverter to the other input terminal of each AND gate of the second pair. The output terminals of the second pair of AND gates are connected to the RESET and SET terminals, respectively, of the master flip-flop.
Normally the input signal to control the operation of the master-slave flip-flop circuit is a square wave having a desired repetition rate. The output signal of the master flip-flop is also a square wave having one-half the repetition rate of the input signal, and the output signal of the slave flip-flop has the same repetition rate as the master flip-flop but is timed to be offset by one-fourth of a complete cycle relative to the master flip-flop output signal.
When it is desired to invert the phase of the master and slave flip-flop circuits one of the input pulses may be eliminated or an additional input pulse may be inserted. However, the duration and the timing of the phase inverting signal must be such that its leading edge occurs when the regular input signal has a "0" value and the inverting signal must terminate after one pulse of the regular input signal has been eliminated and the signal level of the normal timing signal is again at its "0" value. Alternatively, to add an extra control pulse, the additional inverting signal must be quite narrow so that it can start and finish in the same half cycle of the regular timing signal when the regular timing signal has a "0" value. These timing limitations make it difficult to provide a satisfactory inverting operation. The circuit for forming the phase inverting signal must be very complicated, and it is susceptible to noise superimposed on the phase inverting signal.